RF DSP provides products and services to support the deployment of O-RAN, sub-6GHz and mmWave massive MIMO, the most important innovations of 5G RAN. We provide an end-to-end PHY layer System-level Development Environment for O-RAN (O-RAN SDE), O-RU IPs, massive MIMO reference designs and development platform. We also offer customized design and system integration services to speed up your time to market.

O-RAN PHY Layer End-to-End System Development Environment for MIMO O-RUs and O-DUs

A System-Level O-RAN CUSM-Plane Development Environment for Massive MIMO and Small Cell RUs Using Xilinx RFSoC or FPGA + RF Transceivers

Real-Time Physical Layer and Link Layer End-to-End 3GPP and O-RAN Conformance Development Environment for Faster Time-To-Market

RF DSP offers O-RAN Radio Unit (O-RU) IP cores that implements the low PHY baseband functions of the eNB/gNB base station and 7.2x split fronthaul interface to an O-RAN Distributed Unit (O-DU) which implements the high PHY. This O-RU IP includes:

  • O-RAN fronthaul eCPRI/RoE over IP and UDP, supporting 2T2R all the way to 64T 64R massive MIMO.
  • Multiple bands and component carriers, mixed numerology, optional carrier combining with NR + LTE+, LTE-M/NB-IoT and NR mixed numerology support, all with real-time C-plane control.
  • FFT/IFFT and PRACH U-plane processing, IQ compression and decompression, optional beamforming, optional O-RAN Category B.
  • Embedded software processing of PTP 1588 messages and reference S-plane clock recovery circuit.
  • Packet classification of M-plane messages.
  • IQ interfaces: to Ethernet fronthaul, DUC/DDC and RF transceivers
  • Processor interface: for M-plane external CPU processing
  • Radio clock interface: 100Hz radio frame clock input. Optional 100Hz radio frame clock output from the S-plane reference hardware circuit.
  • Optional features and extension types, design services for customization and porting available