RF DSP Inc.

RF DSP provides products and services to support the deployment of O-RAN, sub-6GHz and mmWave massive MIMO, one of the most important innovations in 5G RAN. We provide an end-to-end PHY layer System-level Development Environment for O-RAN (O-RAN SDE), O-RU IPs, massive MIMO reference designs and development platform. We also offer customized design and system integration services to speed up your time to market.

AMD RFSOC Product Line Manager David Brubaker demonstrates RF DSP’s O-RU IP in an O-RAN Conformance Test Setup Using Viavi TM-500 O-DU Emulator and Rohde & Schwartz RF Test Equipment
Hardware setup of RF DSP’s O-RU IP in an O-RAN Conformance Test

RF DSP offers O-RAN Radio Unit (O-RU) IP cores that implements the low PHY baseband functions of the eNB/gNB base station and 7.2x split eCPRI/O-RAN fronthaul interface with an O-RAN Distributed Unit (O-DU) which implements the high PHY. This O-RU IP includes:

  • O-RAN fronthaul eCPRI/RoE over IP and UDP, supporting 2T2R to 64T 64R massive MIMO.
  • Multiple bands and component carriers, mixed numerology, optional carrier combining with NR + LTE+, LTE-M/NB-IoT and NR mixed numerology support, all with real-time C-plane control.
  • FFT/IFFT and PRACH U-plane processing, IQ compression and decompression (block floating point, block scaling and mu-law, static or dynamic), optional beamforming, optional O-RAN Category B.
  • Embedded software processing of PTP 1588 messages and S-plane reference designs.
  • Packet classification of M-plane messages and API to M-plane software.
  • IQ interfaces: to Ethernet fronthaul, DUC/DDC and RF transceivers
  • Processor interface: for M-plane external CPU processing
  • Radio clock interface: 100Hz radio frame clock input. Optional 100Hz radio frame clock output from the S-plane reference hardware circuit.
  • Optional features and extension types, design services for customization and porting available

O-RAN PHY Layer End-to-End System Development Environment for MIMO O-RUs and O-DUs

A System-Level O-RAN CUSM-Plane Development Environment for Massive MIMO and Small Cell RUs Using Xilinx RFSoC or FPGA + RF Transceivers

Real-Time Physical Layer and Link Layer End-to-End 3GPP and O-RAN Conformance Development Environment for Faster Time-To-Market