O-RAN IP Cores
RF DSP offers an O-RAN Radio Unit (O-RU) IP core that implements the low PHY baseband functions of a 5G NR base station and 7.2x split fronthaul interface to an O-RAN Distributed Unit (O-DU) which implements the high PHY. This O-RU IP includes:
Features
- O-RAN fronthaul eCPRI/RoE over IP and UDP, supporting 2T2R all the way to 64T 64R massive MIMO.
- O-RU Category A, non-beamforming baseline configuration
- O-RU Category B and beamforming options including Uplink Performance Improvement (ULPI)
- TDD or FDD
- Multiple bands and component carriers, optional carrier combining with NR + LTE+, LTE-M/NB-IoT and NR mixed numerology support, all with real-time C-plane control.
- Customized component carrier combining / extraction options including DSS, mixed numerology, for different RF interface options
- 5G and 4G DSS support
- Long and short sequence PRACH with multiple time and frequency occasions
- Optional features and extension types, design services for customization and porting available
- IQ streams for up to 4 layers/beam at fronthaul interface and 2, 4 or 8 ADC/DACs at antenna interface
- Channel bandwidth options
- NR: up to 50 / 100 / 200 / 400 MHz
- LTE: 5 / 10 / 20 MHz
- LTE-M: 1.4 MHz
- NB-IoT: 200 kHz
- FR1 and FR2 with SCS of 15kHz, 30kHz, 60kHz and 120kHz, multiple and mixed numerologies Subcarrier spacing options
- NR: 15 / 30 / 60 / 120 kHz
- LTE: 15 kHz
- LTE-M: 15 kHz
- NB-IoT: 3.75 / 15 kHz
- Downlink IFFT and phase rotation for OFDM transmitter
- Uplink FFT and phase rotation for OFDM receiver and PRACH
- IQ compression and decompression with Block Floating Point (BFP), u-Law and Block Scaling
- IQ interfaces: to Ethernet fronthaul, DUC/DDC and RF transceivers
- Processor interface: for M-plane external CPU processing
- Radio clock interface: 100Hz radio frame clock input. Optional 100Hz radio frame clock output from the S-plane reference hardware circuit.
S-plane timing synchronization support
- Packet classification for S-plane PTP 1588 packets and processing in embedded CPU
- Embedded software processing of PTP 1588 messages and reference S-plane clock recovery circuit.
- O-RAN Packet alignment {frame, subframe, slot, symbol} to radio frame clock input
- O-RU S-Plane hardware/software integrated components for all O-RAN defined synchronization topologies C1 through C4 in a reference circuit implementation
M-plane for non-real-time control
- Packet classification for M-plane packets and routing to external CPU interface
- API and command interface to external CPU for configuration and status reporting
Fronthaul interface
- 1x10G, 2x10G, 1x25G, 2x25G Ethernet link options
- eCPRI fronthaul transport, with UDP over IPv4
RF interface
- AXI-streaming IQ sample interface
- Optional customized RF interface option, including DFE (DUC, DDC)
- Optional JESD204B/C interface option to Analog Devices or MaxLinear RF transceivers
O-RAN O-RU SDE (System Development Environment)
- PHY layer end-to-end system environment for optimization, conformance and performance testing of O-RU
- RF DSP O-RU reference hardware, and a second unit for signal playback and capture
- Matlab and C-code running on Linux PC as O-RU Hardware Control, high PHY signal generation and analysis
- O-RAN compliant CUS stimulus with PTP/SyncE
- 3GPP compliant 5G NR waveforms3GPP Channel Models
- O-RAN/eCPRI protocols decode
- IQ extraction & 5G NR modulation EVM, BER and Throughput measurements
- Supports optimization of RF frontend in a PHY layer end-to-end system
- Suite of stock A, B, C, D conformance tests, with source code to support adding custom tests
- Bit exact/accuracy testing with DDR playback and record paths
- Interfaces to integrate custom RF interface modules, including DUC, CFR/DPD, DDC.
- Interfaces to inject external test signals from bench test equipment / O-DU for interoperability testing in simulation and with hardware reference platform.
Please contact sales@rfdsp.com for questions and quotes.