O-RAN PHY Layer End-to-End System Development Environment for MIMO O-RUs and O-DUs

Figure 1.1. Top-level functional block diagram of RFDSP 5G PHY simulation and testing framework

The top-level functional modules and block diagram of RFDSP-SDE is shown in Fig. 1.1. The 5G PHY model, including gNB modules and UE modules are entirely developed by RFDSP using Matlab and C, and verified for conformance with 3GPP and O-RAN specifications using 3GPP references and third-party tools.

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A System-Level O-RAN CUSM-Plane Development Environment for Massive MIMO and Small Cell RUs Using Xilinx RFSoC or SoC FPGA + RF Transceivers

Real-Time Physical Layer and Link Layer End-to-End 3GPP and O-RAN Conformance Development Environment for Faster Time-To-Market

Radio Access Network (RAN) is moving towards open interfaces, software-hardware disaggregation and a CU-DU-RU in an open RAN architecture, led by the O-RAN Alliance (O-RAN). The open fronthaul interface specified by O-RAN Working Group 4 (WG4) is being widely adopted by Mobile Network Operators (MNOs) and RAN equipment vendors. The O-RAN WG4 fronthaul is a 7.2x split interface with low PHY in the O-RU and high PHY in the O-DU. It provides a good balance of reducing fronthaul bandwidth, reducing RU cost and support deployment flexibilities and network optimization. The fronthaul interface comprises the real-time CUS-Planes (Control, User, Synchronization) and the non-real-time M-Plane (Management).

A massive MIMO and small cell MIMO O-RU can be designed either using Xilinx RFSoC, or Xilinx MPSoC or Intel SoC FPGA plus MIMO RF transceivers, e.g., from Analog Devices or MaxLinear. The RFSoC integrates the key subsystems required to implement a complete software-defined radio on a single, highly programmable SoC. The RF frontend functions integrated in the RF transceivers make MPSoC/SoC FPGA + RF Transceivers an excellent choice for O-RUs as well. In either case, the chip vendors offer evaluation tools, GUI and some IP cores that serve as a platform for customers to configure the chips and perform some basic tests to evaluate the RFSoC features, but there is no system level design tools.

The RFDSP SDE provides a system-level tool to support O-RU product development in an end-to-end setting from high PHY and O-RAN fronthaul on a DU emulator to UE PHY emulators. To support RAN equipment vendors to quickly develop and bring to market full-featured massive MIMO and small cell O-RUs and O-DUs using the RFSoCs or SoC FPGA + RF transceivers, a system-level O-RAN CUS-planes and M-plane development environment is needed to enable system, design and test engineers to optimize RF frontend designs, evaluating 3GPP conformance, EVM, BER and throughput impacts of design choices under 3GPP channel conditions, generating test vectors for FPGA/RTL verification, testing O-RAN CUS- and M-plane packet processing, control and monitor of RU performances including configuring the low PHY in real-time using C-plane messages and configuring the RFSoC or RF transceivers from a simulated O-DU using messages over the fronthaul, etc.

The O-RAN WG4 fronthaul is a complicated interface when all the desired features in the specification are included, such as multiple-bands, multiple Component Carriers (CCs), NR and LTE Dynamic Spectrum Sharing (DSS), NB-IoT (in-band, guard band and standalone), mixed numerology, Band-Width Parts (BWPs), MIMO beamforming, the full range of PRACH long and short sequences and formats.

The System-Level O-RAN CUSM-Plane Development Environment developed by RF DSP for Massive MIMO and Small Cell RUs Using RFSoCs (hereafter referred to RFDSP-SDE) meets this need. The functions provided in the RFDSP-SDE are at the system-level above the Xilinx evaluation tool and GUI and incorporates functions of O-RAN fronthaul conformance test equipment. It fills a missing link in the RFSoC development support ecosystem.


  • PHY Algorithms and O-RU Performance Optimization:
    • Integrate into customer system simulation to test RF interface and optimize designs and parameters of DUC, DDC, CFR, DPD, to evaluate impact of design and algorithm choices on EVM and throughput etc.
    • To perform 3GPP conformance tests including ACLR, 3GPP Tx and Rx conformance tests.
    • Support custom testing of MIMO beamforming either using built-in MIMO beamforming algorithms or replacing with custom MIMO algorithms in the high PHY and test the MIMO beamforming performance of the algorithms in the low PHY implementation including EVM, BER, throughput, etc. in a real-time end-to-end PHY environment including built-in 3GPP 3-D MIMO channel models or custom channel conditions
    • To generate hardware floating point test vectors – IQ samples for low PHY datapath, for RTL verification in simulation, end-to-end PHY simulation, DL and UL, including EVM, BER and throughput.
    • Support custom testing of specific algorithms or hardware components, e.g., MIMO calibration and antenna phase alignment, time and frequency offset, phase compensation, PTP timing and 1pps synchronization etc.
    • Support above optimization tests in end-to-end PHY simulation mode or real-time end-to-end PHY hardware emulation mode
  • O-RAN O-RU Conformance and Fronthaul Testing (SDE2):
    • To test O-RU fronthaul CUSM plane interface conformance and O-DU interoperability in simulation mode or real-time hardware emulation mode at end-to-end link layer
    • Real-time emulation mode uses an additional package of Matlab & C code that includes O-RU hardware configuration through Matlab Instrumentation Toolbox, test scripts for custom test and development of O-RAN O-RU conformance and C-code test application running on Linux PC to exercise the real-time fronthaul interface to the O-RU hardware platform. This additional package is provided as source code to provide full customization capability.
    • Reference platform using Xilinx RFSoC Evaluation Boards, with playback and record configuration on UE side to complete the real-time O-RU Conformance test platform, automated running of a list of example “stockA,B,C,D” tests provided with the Matlab/C package.
    • Low level control and IQ debug data paths are provided in the RF DSP O-RU FPGA code, to do custom tests for early development and hardware bring-up, including bit exact tests, digital and RF loopback tests, RF playback and record etc. Test examples that exercise these options are provided in the RFDSP SDE2 code.
    • To prove O-RU interoperability with commercial O-DUs and bench test equipment (e.g. Keysight O-RAN studio), the RFDSP-SDE signal generation and analysis stages can be replaced with corresponding O-DU/bench test equipment at RF or fronthaul interface. This can also be done in simulation using file input/output at any interface point in the UL or DL datapath. Pcap file support is provided for testing with Keysight O-RAN Studio.
  • O-DU Testing:
    • The O-RAN O-RU conformance test model can be used to support O-DU conformance testing and development, in both simulation and real-time hardware platform. Where the C-code running on Linux PC that exercises the real-time fronthaul interface to the O-RU could be replaced with a real O-DU, and Matlab source code provided with the RFDSP-SDE could be modified to configure the O-DU in the test loop.
    • Similarly, the RFDSP-SDE UE Emulator platform (doing IQ playback and record) can be replaced in the test environment with real UEs.
    • RF DSP can provide customization service for the SDE O-RU test and development environment for these cases as required.

Fig. 1.2 below shows the modules, interfaces and signal flow of the RFDSP SDE and how it can be used with or in place of third-party O-RAN conformance test tools such as Keysight’s O-RAN Studio to test O-RAN conformance. Note that the RFDSP SDE offers more functions and flexibility than third-party O-RAN conformance test tools. RFDSP SDE supports interface to customer’s RF DFE and filter designs for system-level end-to-end RF performance measurements and optimization, internal test vector generation for testing interfaces and intermediated data path stages in the PHY, O-RU testing in real-time hardware emulation, and can be extended for O-DU test and development.

Figure 1.2. Modules, interfaces and signal flow of the RFDSP SDE to support O-RU design, simulation, testbench generation and debug. It also shows how the SDE is used with or in place of third-party O-RAN conformance test tools. Keysight Open RAN Studio is used as an example.

In-System Optimization of RF Performance

Fig.1.3 below highlights a comparison of RFDSP SDE with third-party O-RAN conformance test tools on the market. The solid black line boxes are functions provided by both RFDSP SDE and third-party O-RAN conformance tools. In the dash-dot line box, in addition to generates O-RAN CSU-plane stimulus as third-party O-RAN conformance tools, RFDSP SDE also supports integration and testing of customer algorithms or O-DU fronthaul inputs.  RF DSP also provides O-RU hardware IPs, hardware models of both high and low PHY.

Fig.1.3. Highlights of a comparison of functions and components of RFDSP SDE and third-party O-RAN conformance test tools on the market.

As shown in the dashed line box enclosing the two green DFE modules in the center in Fig. 1.3, RFDSP SDE provides interfaces to integrate customer DFE algorithms and filter designs. This enables testing and optimization of customer’s DFE designs including DUC, DDC, CFR, DPD and channel filters for ACLR in an end-to-end complete PHY-layer system setting to measure and ensure EVM, BER and Throughput performance.

O-RAN Conformance

Fig. 1.4. Typical Interoperability Testing Scenarios using RFDSP O-RAN SDE

Fig. 1.4 shows how RFDSP SDE can be used in conjunction with a third-party O-RAN test tool such as Keysight O-RAN Studio or in place of the third-party test tool to test O-RAN conformance.

O-RU Internal Test Vector Generation

As shown in the dashed line box at the bottom in the center in Fig. 1.3, the O-RU IP Development Testbench module in the RFDSP SDE generates internal test vectors covering any point in the control or data paths of the O-RU IP, including the low PHY with PRACH, the fronthaul, the interface between the fronthaul and the low PHY and the RF interface. Fig. 1.5 below shows examples of internal test points along DL, UL and PRACH data paths for which the SDE generate test vectors to ensure test coverage, performance along the data paths and facilitate debug. 

Fig. 1.5. Examples of internal test points along DL, UL and PRAH data path, for which the SDE generated test vectors to ensure test coverage, performance along the data paths and facilitate debug.

Real-Time Hardware Emulation of O-RU

Furthermore, the RFDSP SDE supports real-time testing of O-RU in an end-to-end PHY layer system setting in hardware emulation, as shown in Fig. 1.6 below. This platform goes beyond simulation to prove the O-RU IP in high data rate real-time operation, more efficiently and more effectively detect bugs and performance issues to ensure timing, latency, PHY and RF performance.  

Fig. 1.6. Real-time Hardware Emulation using RFDSP SDE to support real-time testing of O-RU in an end-to-end PHY layer system setting.


RF DSP offers O-RU IPs with an extensive feature list covering the O-RAN WG4 CSU-plane specification v5.0. The IPs are modeled, verified and tested using the RFDSP SDE described above.

Please contact sales@rfdsp.com for quotes and questions.